Pre-Silicon Verification Engineer

This role involves verifying complex interconnects and configurable switches at the IP or SoC level using SystemVerilog and UVM. The engineer will debug RTL code, develop verification environments, and mentor junior team members.

• Develop and enhance verification testbenches
• Debug RTL code
• Verify configurable switches
• Mentor junior engineers
• Collaborate with design teams

Focus on ASIC verification, SystemVerilog, UVM, RTL debugging, and simulation on Linux and Windows platforms, with an emphasis on verification of interconnect architectures.

The ideal candidate is a senior verification engineer with extensive experience in SystemVerilog, UVM, and ASIC verification. They should have strong debugging skills, experience mentoring junior engineers, and familiarity with simulation environments on Linux and Windows.