Position Details
About this role
This role involves verifying complex interconnect designs at the IP or SoC level using SystemVerilog and UVM, developing and enhancing testbenches, and mentoring junior engineers in a collaborative environment.
Key Responsibilities
- Develop testbenches
- Debug test failures
- Collaborate with architects and RTL designers
- Enhance verification environment
- Mentor junior engineers
Technical Overview
The technical scope includes ASIC verification, SystemVerilog, UVM, RTL debugging, simulation tools, and coverage analysis within a hybrid Linux/Windows environment.
Ideal Candidate
The ideal candidate is a senior verification engineer with 3+ years experience in ASIC or IP level verification, proficient in SystemVerilog and UVM, with strong debugging and testbench development skills. They should be collaborative, detail-oriented, and capable of mentoring junior engineers.
Must-Have Skills
Nice-to-Have Skills
Tools & Platforms
Required Skills
Hard Skills
Soft Skills
Industry & Role
Keywords for Your Resume
Deal Breakers
Lack of experience with SystemVerilog or UVM, No ASIC verification background, Inability to work in a hybrid environment, No experience with simulation tools
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