Position Details
About this role
This role involves leading the development of FPGA place and route tools, focusing on timing, congestion, and verification to support high-performance FPGA designs.
Key Responsibilities
- Manage FPGA place and route processes
- Optimize timing and congestion
- Develop bitstream tools
- Lead verification efforts
- Manage team activities
Technical Overview
Focus on FPGA backend development, including place and route, timing analysis, bitstream generation, and silicon debug, with leadership in verification methodologies.
Ideal Candidate
The ideal candidate is a senior engineer with extensive FPGA backend development experience, specializing in place and route, timing analysis, and silicon debug. Leadership in FPGA tool development and verification is essential.
Must-Have Skills
Nice-to-Have Skills
Tools & Platforms
Required Skills
Hard Skills
Soft Skills
Industry & Role
Keywords for Your Resume
Deal Breakers
Lack of FPGA backend tools experience, No experience with timing-driven implementation, Inability to manage teams or projects
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