Product Line Manager, EPYC Server CPUs

Analog Design Engineer for PLL/adaptive clocking to define and implement PLL IPs powering AMD products. You will run pre-tapeout verification, collaborate with mask/design and post-silicon teams, and mentor junior engineers.

• Design PLL building blocks including architecture development and transistor-level circuit design
• Run pre-tapeout verification flows to meet performance, power, reliability and timing requirements
• Work with mask design to deliver physical design and test plans with post-silicon groups
• Lead/mentor junior engineers

Scope includes PLL/IP block design in FinFET nodes (16/14/10/7nm), Cadence ADE tools, Monte Carlo/noise/aging simulations, and DC/AC verification with Calibre/ICV; requires proficiency in SPICE-like tools (Spectre, HSPICE) and scripting (Python/Perl/Tcl).

The ideal candidate is an experienced analog design engineer with deep PLL expertise, FinFET process experience, and a strong grasp of verification and timing. They should be comfortable leading junior engineers, performing pre-tapeout verification, and collaborating with mask design and post-silicon teams.