Position Details
About this role
This role involves designing advanced silicon IP blocks for AI/ML and cloud data centers, focusing on front-end RTL design, debugging, and verification.
Key Responsibilities
- Design complex IP blocks
- Debug silicon designs
- Collaborate with global teams
- Develop RTL code
- Verify design functionality
Technical Overview
Focuses on RTL and ASIC design using Verilog and VHDL, scripting automation with Python and Perl, and developing high-performance silicon for AI/ML applications.
Ideal Candidate
The ideal candidate is a senior IC design engineer with extensive experience in RTL, ASIC, and digital design, proficient in Verilog and VHDL, with scripting skills in Python and Perl, capable of working on advanced AI/ML hardware projects.
Must-Have Skills
Nice-to-Have Skills
Tools & Platforms
Required Skills
Hard Skills
Soft Skills
Industry & Role
Keywords for Your Resume
Deal Breakers
Lack of industry experience in RTL/ASIC design, No proficiency in Verilog or VHDL, Unwilling to work at specified locations
Get matched to jobs like this
Luna finds roles that fit your skills and career goals — no endless scrolling required.
Create a Free Profile