✦ Luna Orbit — Engineering (Non-Software)

R&D Hardware Design Engineer (High Speed Analog)

at Broadcom

📍 USA-CA Irvine Alton Parkway Bldg 2 Unknown 💰 $108K – $172K USD / year Posted March 13, 2026
Salary $108K – $172K USD / year
Type Not Specified
Experience mid
Exp. Years 6+ years
Education Bachelor's in Engineering/Computer Science or Master's in Engineering/Computer Science
Category Engineering (Non-Software)

This role involves designing and developing high-speed analog circuits for wireline transceivers, focusing on high-speed ADC/DAC, PLL, and jitter performance.

  • Design high-speed ADC/DAC circuits
  • Develop PLL and jitter reduction techniques
  • Evaluate and select components
  • Perform experimental testing
  • Collaborate on high-frequency system development

Focus on high-speed analog circuit design, PLL, jitter reduction, laser drivers, and high-frequency system components, utilizing CAD tools for simulation and layout.

The ideal candidate is an experienced analog design engineer with 6+ years in high-speed circuit design, specializing in ADC/DAC, PLL, and jitter reduction, with strong CAD tool proficiency.

High-Speed ADC and DAC DesignPLL DesignLow Jitter DesignLaser Driver DesignHigh-Speed Analog Circuit Design
Backplane EqualizationOptical Link TechniquesClock & Data RecoveryHigh Linearity Design
CAD toolsHigh-Speed ADC/DAC simulation toolsPLL design tools
High-Speed ADCHigh-Speed DACPLLLow JitterLaser DriverHigh Speed Analog DesignClock & Data RecoveryCAD tools
High-Speed ADCHigh-Speed DACPLLLow JitterLaser DriverEqualization TechniquesClock & Data Recovery CircuitsCAD toolsAnalog Circuit DesignHigh Speed Design
Design AnalysisExperimental TestingComponent SelectionVendor ReviewProblem SolvingCollaboration
Industry Semiconductors & Electronics
Job Function Design high-speed analog and mixed-signal circuits for advanced transceiver systems
High-Speed ADCHigh-Speed DACPLLLow JitterLaser DriverHigh Speed Analog DesignClock & Data RecoveryBackplane EqualizationOptical LinksCAD toolsHigh Speed Analog Circuit

Lack of experience with high-speed analog design, No background in PLL or jitter reduction, Inadequate knowledge of high-speed transceiver components

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