✦ Luna Orbit — Engineering (Non-Software)

R&D Hardware Engineer (High Speed Analog)

at VMware

📍 2 Locations Unknown 💰 $108K – $192K USD / year Posted March 13, 2026
Salary $108K – $192K USD / year
Type Full-Time
Experience mid
Exp. Years 5+ years
Education Bachelor's degree in Engineering/Computer Science and 5+ years of related experience or Masters degree in Engineering/Computer Science and 3+ years of related experience
Category Engineering (Non-Software)

This position involves designing high-speed analog components for multiple locations, focusing on signal integrity and high-frequency performance in wireline transceivers.

  • Design high-speed analog circuits
  • Evaluate electronic components
  • Analyze equipment performance
  • Review vendor capabilities
  • Collaborate with cross-functional teams

Expertise in high-speed analog circuit design, PLLs, jitter reduction, optical communication, and CAD tools for hardware development across various locations.

The ideal candidate is a mid-level hardware engineer with experience in high-speed analog circuit design, supporting multiple locations with expertise in PLLs, jitter reduction, and optical communication components.

High-Speed ADC and DAC DesignPLL DesignLow Jitter PLLAnalog Circuit Design
Optical LinksBackplane EqualizationLaser Driver DesignData Recovery Circuits
CAD tools
High-Speed ADCDACPLL DesignLow JitterAnalog Circuit DesignOptical LinksBackplane EqualizationLaser DriverData RecoveryCAD tools
High-Speed ADCAnalog Circuit DesignDACPLL DesignLow JitterTHDEqualization TechniquesClock & Data RecoveryCAD tools
Problem-solvingJudgmentRelationship BuildingAnalysisCollaboration
Industry Technology
Job Function Develop high-speed analog hardware for communication systems across multiple sites
High-Speed ADCAnalog Circuit DesignDACPLL DesignLow JitterTHDOptical LinksBackplane EqualizationLaser DriverClock & Data RecoveryCAD toolsHigh-Speed (>10Gbps)High-Speed (>28GHz)Low Jitter (<100fs-rms)Data Recovery

Less than 3 years of relevant experience, Lack of experience with high-speed analog design, No background in PLL or jitter reduction, No degree in Engineering or related field

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