About this role
Develop and optimize ATE test software and methodologies for Amazon Leo custom silicon used in LEO satellite phased array antennas and ground terminal products. Own RF/mixed-signal test routines, on-chip calibration and OTP memory test strategies, and production test feature validation.
Key Responsibilities
- Implement and optimize RF, mixed signal, and high-speed interface test routines for high-volume manufacturing
- -Design, develop, and verify on-chip calibration techniques and ATE calibration methodologies
- -Develop and execute test strategies for on-chip one-time programmable (OTP) memory
- -Validate on-chip test features including built-in self-test (BIST), scan chains, JTAG, and design-for-test (DFT) structures
- -Optimize ATE test time with parallel testing strategies, adaptive test algorithms, and intelligent test flow sequencing using SPC and correlation analysis
Technical Overview
You will build modular ATE test solutions for high-volume manufacturing, including characterization/validation for mm-wave RFICs, calibration across process/voltage/temperature (PVT) corners, and OTP memory verification. The role includes production test enablement using BIST, scan chains, JTAG, and DFT structures, plus test-time optimization with parallel/adaptive algorithms and statistical process control (SPC).
Ideal Candidate
The ideal candidate is a mid-level ATE Test Engineer with 3+ years developing RF and analog silicon test solutions for high-volume manufacturing. They have hands-on experience with mm-wave RFIC characterization, on-chip calibration across PVT corners, OTP memory test strategies, and production debug/optimization using ATE platforms like Uflex or Advantest.
Must-Have Skills
Bachelor's degree in Electrical Engineering or a related field3 or more years of employment in ATE test development focused on RF and Analog siliconImplement and optimize RFmixed signaland high-speed interface test routines for high-volume manufacturingDesigndevelopand verify on-chip calibration techniquesDevelop and execute test strategies for on-chip one-time programmable (OTP) memoryCollaborate with system architecture and design teams to defineimplementand validate on-chip test features including built-in self-test (BIST)scan chainsJTAG interfacesand design-for-test (DFT) structuresOptimize ATE test time through parallel testing strategiesadaptive test algorithmsand intelligent test flow sequencing while maintaining data quality standards through statistical process control (SPC)outlier detectionand correlation analysis
Nice-to-Have Skills
Master's degree or Ph.D. in Electrical Engineering or related field5+ years of experience debugging complex test failuresDeveloping and optimizing ATE code for Uflex or Advantest platformsDebugging complex test failuresBringing u (truncated in posting; inferred as continuing experience with Uflex/Advantest and test program architecture)
Tools & Platforms
ATEUflexAdvantestJTAGbuilt-in self-test (BIST)design-for-test (DFT)statistical process control (SPC)
Required Skills
ATE test developmentRFmixed signalhigh-speed interface test routinesmm-wave RFIC characterization/validationmodular test solutionshigh-volume production test methodologyon-chip calibration techniquescalibration algorithmsPVT cornersone-time programmable (OTP) memory testingprogramming mechanismsbit yield optimizationprogramming voltage marginsredundancy schemespost-programming reliability validationbuilt-in self-test (BIST)scan chainsJTAG interfacesdesign-for-test (DFT) structuresparallel testing strategiesadaptive test algorithmsintelligent test flow sequencingstatistical process control (SPC)outlier detectioncorrelation analysisUflexAdvantesttest program architecture design
Hard Skills
ATE test developmentRF testmixed signal testhigh-speed interface testmm-wave RFIC characterizationvalidation test methodologymodular test solutionshigh-volume production testingcharacterization/validation test methodology of mm-wave RFICson-chip calibration techniquescalibration algorithmsvalidation of calibration accuracy across process/voltage/temperature (PVT) cornersATE test methodologiesanalog and mixed-signal circuit teston-chip one-time programmable (OTP) memory testingprogramming mechanismsverification methodologiesbit yield optimizationprogramming voltage marginsredundancy schemespost-programming reliability validationbuilt-in self-test (BIST)scan chainsJTAG interfacesdesign-for-test (DFT) structuresproduction test coveragedebug and failure analysisparallel testing strategiesadaptive test algorithmsintelligent test flow sequencingstatistical process control (SPC)outlier detectioncorrelation analysisUflex test platformsAdvantest platformstest program architecture design
Soft Skills
ResponsiveFlexibleComfortable in an open collaborative peer environmentAbility to succeed in cross-disciplinary staff collaborationExcellent oral and written communications skillsAbility to convey complex technical information effectivelyAbility to define and develop innovative test software solutions
Keywords for Your Resume
RF ATE EngineerATE Test EngineerATE test developmentRFmixed signalhigh-speed interfacemm-wave RFICsAmazon Leo phased array antennasLEO satellitesground terminal productscharacterization/validation test methodologymodular test solutionshigh-volume productionon-chip calibration techniquescalibration algorithmsprocess/voltage/temperature (PVT) cornersbuilt-in self-test (BIST)scan chainsJTAGdesign-for-test (DFT)one-time programmable (OTP) memoryprogramming mechanismsbit yield optimizationprogramming voltage marginsredundancy schemespost-programming reliability validationparallel testing strategiesadaptive test algorithmsintelligent test flow sequencingstatistical process control (SPC)outlier detectioncorrelation analysisUflexAdvantesttest program architecture design
Deal Breakers
Bachelor's degree in Electrical Engineering or a related field, 3 or more years of ATE test development focused on RF and Analog silicon, Must meet Export Control Requirement (U.S. citizen or national, U.S. permanent resident, or lawfully admitted as a refugee/asylum)
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