Position Details

Salary $108K – $172K USD / year

Type Not Specified

Experience senior

Exp. Years 8+ years

Education Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Science, or Computer Engineering

Category Engineering (Non-Software)

About this role

This role involves designing and supporting high-performance RTL for next-generation data center hardware, including PCIe switches and storage solutions, with a focus on timing closure and complex digital architectures.

Key Responsibilities

RTL architecture analysis
RTL implementation
Timing closure
RTL debugging
Collaborate with verification and software teams

Technical Overview

The position requires extensive RTL development in Verilog/SystemVerilog, managing timing closure, debugging, and integrating third-party IP for enterprise storage and AI/ML data center applications.

Ideal Candidate

The ideal candidate is a senior digital IC design engineer with over 8 years of experience in RTL development, verification, and timing closure. They have deep expertise in Verilog/SystemVerilog, high-performance digital design, and integration of third-party IP for data center applications.

Must-Have Skills

RTL DesignVerilog/SystemVerilogTiming closureRTL debuggingASIC/FPGA designHigh-performance digital design

Nice-to-Have Skills

CXL protocolPCIe protocolAMBA protocolsRAID StoragePCIe SwitchDeep computationsMulti-clock domain design

Tools & Platforms

VerilogSystemVerilogRTL design toolsTiming analysis toolsSimulation tools

Required Skills

RTL DesignVerilogSystemVerilogTiming closureRTL debuggingASIC/FPGA designHigh-performance digital designCXL protocolPCIe protocolRAID StoragePCIe Switch

Hard Skills

RTL DesignVerilogSystemVerilogRTL implementationTiming closureRTL debuggingASIC/FPGA designHigh-performance digital designPower managementMulti-clock domain designDeep computationsPipeliningThird-party IP integrationCXL protocolPCIe protocolAMBA protocolsRAID StoragePCIe Switch

Soft Skills

Analytical skillsProblem-solvingCollaborationCommunicationAttention to detail

Industry & Role

Industry Semiconductor & Data Center Hardware

Job Function Design and verify high-performance RTL for data center ASICs and FPGAs

Keywords for Your Resume

RTL DesignVerilogSystemVerilogRTL implementationTiming closureRTL debuggingASIC designFPGA designHigh-performance digital designPower managementMulti-clock domainDeep computationsPipeliningThird-party IPCXL protocolPCIe protocolAMBA protocolsRAID StoragePCIe SwitchASIC/FPGA design

Deal Breakers

Less than 8 years of relevant experience, Lack of RTL design or debugging skills, No experience with Verilog or SystemVerilog, No background in ASIC/FPGA design

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RTL IC Design Engineer

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