Position Details

Salary $108K – $172K USD / year

Type Full-Time

Experience senior

Exp. Years 8+ years

Education Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Science, or related field

Category Engineering (Non-Software)

About this role

This role involves designing, optimizing, and debugging RTL for next-generation AI/ML data center hardware, supporting PCIe, CXL, and other high-speed protocols in a senior engineering capacity.

Key Responsibilities

RTL design and implementation
Timing closure
RTL debugging
Protocol support
Cross-team collaboration

Technical Overview

The position requires extensive RTL development in Verilog/SystemVerilog, timing closure, protocol support, and collaboration with verification and validation teams for high-performance ASIC/FPGA designs.

Ideal Candidate

The ideal candidate is a senior digital IC design engineer with over 8 years of experience in RTL development, verification, and debugging, with strong knowledge of PCIe, CXL, and AMBA protocols, and experience supporting high-performance ASIC or FPGA designs.

Must-Have Skills

RTL designVerilog/SystemVerilogTiming closureRTL debuggingASIC/FPGA design

Nice-to-Have Skills

PCIe protocolCXL protocolAMBA protocolsRAID StorageVerificationFirmwareEmulation

Tools & Platforms

VerilogSystemVerilogRTL simulation toolsTiming analysis toolsEmulation platforms

Required Skills

RTL DesignVerilogSystemVerilogTiming closureRTL debuggingASIC/FPGA designPCIeCXLAMBARAID Storage

Hard Skills

RTL DesignVerilogSystemVerilogRTL optimizationTiming closureRTL debuggingASIC/FPGA designDigital IC designPCIe protocolCXL protocolAMBA protocolsRAID StorageVerification EngineeringFirmware EngineeringEmulation EngineeringValidation Engineering

Soft Skills

Analytical thinkingProblem-solvingCollaborationCommunicationAttention to detail

Industry & Role

Industry Data Center & Semiconductor

Job Function Design and optimize RTL for advanced data center ICs

Keywords for Your Resume

RTL DesignVerilogSystemVerilogRTL optimizationTiming closureRTL debuggingASIC designFPGA designPCIe protocolCXL protocolAMBA protocolsRAID StorageVerification EngineeringEmulation EngineeringValidation EngineeringASIC/FPGA designVerificationEmulationPCIe

Deal Breakers

Less than 8 years of relevant experience, Lack of experience with Verilog/SystemVerilog, No background in RTL debugging or timing closure, No knowledge of PCIe or high-speed protocols

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RTL IC Design Engineer

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