Position Details
About this role
This role involves leading the development and integration of AI-driven tools for ASIC design and verification, focusing on accelerating verification workflows and deploying formal methods. The engineer will work across digital architecture, embedded software, and verification domains.
Key Responsibilities
- Develop AI-driven verification tools
- Integrate AI/ML into ASIC workflows
- Deploy formal verification methods
- Connect AI tools with engineering domains
- Enhance verification accuracy
Technical Overview
The technical environment includes ASIC design, SystemVerilog, UVM, formal verification tools, and AI/ML frameworks to enhance hardware verification processes and digital design workflows.
Ideal Candidate
The ideal candidate is an experienced ASIC design and verification engineer with strong knowledge of AI and ML applications in hardware development. They should have expertise in SystemVerilog, UVM, and formal verification, with the ability to develop AI-driven verification tools and connect them across engineering domains.
Must-Have Skills
Nice-to-Have Skills
Tools & Platforms
Required Skills
Hard Skills
Soft Skills
Industry & Role
Keywords for Your Resume
Deal Breakers
Lack of ASIC design or verification experience, No knowledge of AI/ML applications, No experience with SystemVerilog or UVM, Lack of problem-solving skills in hardware verification
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