Position Details

Type Full-Time

Experience senior

Exp. Years 7+ years

Education Not specified

Category Engineering (Non-Software)

About this role

Senior ASIC Design Infrastructure & Methodologies engineer to automate design flows and build large-scale solutions to accelerate silicon development for MLA chips. Works with cross-functional teams to refine flows and evaluate new design tools and tool versions.

Key Responsibilities

Develop and implement new methodologies and infrastructure to empower design teams to operate efficiently while maintaining high-quality standards
Enhance and build design flows to boost productivity
Collaborate with vendors to evaluate and qualify new design tools and tool versions
Collaborate with architects, designers, verification engineers to refine flows
Lead automation initiatives for Post-Silicon Flow

Technical Overview

Focus on RTL design, ASIC implementation, synthesis, STA, physical design for 16nm+ nodes; develops automation frameworks for Post-Silicon Flow; supports post-silicon validation and SOC bring-up; experience in wireless and RF layout.

Ideal Candidate

The ideal candidate is a senior ASIC design infrastructure engineer with 7+ years in ASIC implementation, RTL and automation, adept at building scalable design flows and Post-Silicon Flow automation. They should have deep experience in wireless and RF layout, verification, and cross-functional collaboration with architects, designers, and verification teams.

Must-Have Skills

ASIC implementationSynthesisSTAPhysical designdeep sub-micron nodes (16nm or smaller)digital design in communication systemsfull-custom analog or RF layoutwireless communications systemsUVMCSystem CscriptingRTL codingSOC bring-uppost-silicon validationautomation frameworks for Post-Silicon Flowverification in communication systems

Nice-to-Have Skills

Master's degree or Ph.D.RTL coding and debugexperience with modern ASIC/FPGA design and verification toolsSOC bring-up and post-silicon validation

Required Skills

ASIC implementationsynthesisSTAphysical designdeep sub-micron nodes (16nm or smaller)digital design in communication systemsfull-custom analogRF layoutwireless communications systemsautomation frameworksPost-Silicon Flowverification in communication systemsUVMCSystem CscriptingRTL codingSOC bring-uppost-silicon validation

Hard Skills

ASIC implementationsynthesisSTAphysical designdeep sub-micron nodes (16nm or smaller)digital design in communication systemsfull-custom analogRF layoutwireless communications systemsautomation frameworks for Post-Silicon FlowPost-Silicon Flowverification in communication systemsUVMCSystem CscriptingRTL codingSOC bring-uppost-silicon validationASIC/FPGA design

Soft Skills

collaborationcommunicationteamworkproblem-solvinginitiativeattention to detailcross-functional leadershipownershipadaptability

Industry & Role

Industry Manufacturing

Job Function Design infrastructure and methodologies for ASIC design automation and optimization

Role Subtype Electrical Engineer

Keywords for Your Resume

ASIC implementationsynthesisSTAphysical designdeep sub-micron nodes (16nm or smaller)digital design in communication systemsfull-custom analogRF layoutwireless communicationsautomation frameworks for Post-Silicon FlowPost-Silicon Flowverification in communication systemsUVMCSystem CscriptingRTL codingSOC bring-uppost-silicon validationScripting

Deal Breakers

No ASIC implementation experience, No deep sub-micron node experience, No automation framework experience

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