Position Details

Salary $149K – $284K USD / year

Type Not Specified

Experience senior

Exp. Years 8+ years (Bachelor); 6+ years (Master); 3+ years (PhD)

Education Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field

Category Software Engineering

About this role

Senior Density Fill Development Engineer at Intel designs and implements density fill components within PDKs to ensure manufacturability, automates workflows, and collaborates with process developers and external EDA vendors to push density solutions for advanced nodes.

Key Responsibilities

Design, develop, and debug Fill components of Process Design Kits (PDKs)
Provide algorithmic solutions using Calibre, ICV, and Pegasus to address density deficiencies
Collaborate with process developers, design rule owners, and end users to define requirements
Automate workflows to enhance efficiency and deployment across design teams
Maintain documentation, including training materials and user guides

Technical Overview

Role centers on EDA tool development for density fill and PDK tooling, using Calibre/ICV/Pegasus, scripting in Python/Tcl/Perl, and cross-functional collaboration with process and design teams to address density-related manufacturability constraints.

Ideal Candidate

The ideal candidate is a senior density fill engineer with 8+ years of experience in EDA tools development, strong scripting (Python/Tcl/Perl), and deep expertise in Calibre, ICV, Pegasus, and PDKs. They will lead tool development affecting density fill and manufacturability for Intel Foundry.

Must-Have Skills

Bachelor's degree in Electrical EngineeringComputer Engineeringor a related field8+ years of relevant experience (Bachelor); 6+ years with Master's; 3+ years with PhDProficiency in scripting languages such as PythonTclor Perl for automationExpertise in EDA toolsincluding CalibreICVor Pegasuswith rule deck developmentUnix/Linux platformsAlgorithmic solutions for physical design challengesStrong knowledge of semiconductor device physics and design rules

Nice-to-Have Skills

Cadence VirtuosoSynopsys Custom DesignerDRCdensity/fill modulestechnology scaling challenges

Tools & Platforms

CalibreICVPegasusSVRF/TVFPXLPVL/PVTCLCadence VirtuosoSynopsys Custom DesignerUnix/Linux

Required Skills

PythonTclPerlCalibreICVPegasusSVRF/TVFPXLPVL/PVTCLUnix/LinuxCadence VirtuosoSynopsys Custom DesignerProcess Design Kits (PDKs)PDKdensity/fillDRCalgorithmic solutionsphysical design

Hard Skills

PythonTclPerlCalibreICVPegasusSVRF/TVFPXLPVL/PVTCLUnix/LinuxCadence VirtuosoSynopsys Custom DesignerProcess Design Kits (PDKs)PDKdensity/fillDRCalgorithmic solutionsphysical design

Soft Skills

CollaborationAnalytical thinkingCommunicationLeadershipProblem-solvingCross-functional teamworkDocumentation

Industry & Role

Industry Manufacturing

Job Function EDA tools software engineer focusing on density fill and PDK tooling for Intel Foundry

Role Subtype software engineer

Tech Domains Python, Tcl, Perl, EDA tools, Unix/Linux, Cadence Virtuoso, Synopsys Custom Designer

Keywords for Your Resume

PythonTclPerlCalibreICVPegasusSVRF/TVFPXLPVL/PVTCLUnix/LinuxCadence VirtuosoSynopsys Custom DesignerProcess Design Kits (PDKs)PDKdensity/fillDRCalgorithmic solutionsphysical designEDA toolsdensity fillautomationsilicon manufacturingProcess Design Kits

Deal Breakers

Lack of 8+ years experience (or 6+ with Master's, or 3+ with PhD), No experience with Calibre, ICV, Pegasus, No scripting (Python/Tcl/Perl), No Unix/Linux knowledge, No EDA tooling experience

Apply for this Position →

Get matched to jobs like this

Luna finds roles that fit your skills and career goals — no endless scrolling required.

Create a Free Profile