✦ Luna Orbit — System Administration

Senior Formal Verification Engineer - AI SoC Development

at Intel

📍 4 Locations Hybrid 💰 $220K – $311K USD / year Posted March 13, 2026
Salary $220K – $311K USD / year
Type Not Specified
Experience senior
Exp. Years 7+ years
Education Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science
Category System Administration

This role involves leading formal verification efforts for complex ASIC and SoC designs, utilizing advanced formal methods, tools, and scripting to ensure functional correctness and coverage closure.

  • Own formal verification strategy
  • Develop verification environments
  • Write formal properties
  • Collaborate with design teams
  • Drive coverage closure

The position requires expertise in formal verification methodologies, tools like JasperGold, UVM, and scripting languages, supporting pre-silicon validation and debug processes.

The ideal candidate is a senior formal verification engineer with over 10 years of ASIC/SoC verification experience, proficient in formal methods, verification tools like JasperGold, and scripting skills, capable of leading complex verification projects.

Bachelor's degree in Electrical EngineeringComputer Engineeringor Computer Science10+ years of ASIC/SoC verification3+ years focused on formal verificationExperience with formal verification tools (e.g.JasperGoldVC FormalQuesta Formal)
UVM-based simulationDigital design conceptsClock domain crossingsLow-power design techniquesScripting skills (PythonTCLPerl)
JasperGoldVC FormalQuesta FormalSystemVerilog AssertionsUVMSimulation tools
Formal verificationSystemVerilog AssertionsASIC verificationSoC verificationCoverage analysisEmulationSystem simulationUVMPythonTCLPerlDebuggingPre-silicon validation
Formal verificationSystemVerilog AssertionsASIC verificationSoC verificationVerification environmentsCoverage analysisEmulationSystem simulationUVMPythonTCLPerlDebuggingPre-silicon validation
LeadershipCollaborationProblem-solvingCommunicationAttention to detail
Industry Semiconductor / ASIC Verification
Job Function Formal verification of ASIC/SoC designs using advanced methodologies and tools
Formal verificationSystemVerilog AssertionsASIC verificationSoC verificationCoverage analysisEmulationSystem simulationUVMPythonTCLPerlDebuggingPre-silicon validationJasperGoldVC FormalQuesta FormalFormal verification toolsASIC/SoC verificationFormal sign-offCoverage closure

Less than 7 years of verification experience, No experience with formal verification tools like JasperGold or VC Formal, Lack of scripting skills (Python, TCL, Perl), No relevant degree

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