Position Details

Salary $115K – $219K USD / year

Type Full-Time

Experience senior

Exp. Years 3+ years

Education Bachelor's degree in Electrical Engineering, Chemical Engineering, Materials Science, Industrial/Mechanical Engineering, or related field (or higher)

Category Engineering (Non-Software)

About this role

Senior Manufacturing Mask Design Engineer at Intel Foundry Technology Development focuses on layout integration for frame cellsets, ensuring frame-related data supports product fabrication. The role requires strong CAD tool experience and close collaboration with Process Technology Development and Mask Operations to drive tapeout readiness.

Key Responsibilities

Layout Integration
Data validation XOR analysis
Technical consultation
Quality assurance of frame placement
Document frame revisions and NPI setup

Technical Overview

Technical scope includes frame cellset integration, XOR analysis, design rule verification, lithography and metrology, UNIX-based tooling, and frame data output management across multiple process technologies.

Ideal Candidate

The ideal candidate is a senior frame cellset owner with 3+ years of semiconductor manufacturing experience and strong CAD tool proficiency (Cadence Virtuoso, Calibre). They should be proficient in UNIX and shell scripting, with the ability to collaborate across process technology development and tapeout operations.

Must-Have Skills

3 to 5+ years of semiconductor manufacturing experiencePhD in Electrical EngineeringChemical EngineeringMaterials ScienceIndustrial/Mechanical Engineeringor related field OR Masters with 3+ years OR Bachelors with 4+ yearsExperience in semiconductor manufacturing processesparticularly lithography and metrologyCadence Virtuoso and Calibre experienceUNIX and shell scripting

Nice-to-Have Skills

Experience with CAD layout tools (Cadence VirtuosoCalibre preferred)Proficiency in UNIX computing environments and shell programming

Tools & Platforms

Cadence VirtuosoCalibre design softwareUNIXshell scripting

Required Skills

3 to 5+ years of semiconductor manufacturing experienceexperience with lithography and metrologyCadence VirtuosoCalibreUNIXshell scriptingXOR analysisdesign rule verificationtapeoutframe cellset ownershipprocess technology development

Hard Skills

Cadence VirtuosoCalibre design softwareUNIXshell programminglithographymetrologyframe data outputtapeoutdesign rule verificationXOR analysissemiconductor manufacturingProcess Technology DevelopmentProduct Design teamsMask OperationsNPI setup

Soft Skills

analyticalattention to detailcollaborativecommunicationproblem solvingself-motivated

Industry & Role

Industry Manufacturing

Job Function Frame cellset layout integration for semiconductor mask design and tapeout readiness

Role Subtype Manufacturing Engineer

Keywords for Your Resume

Frame Cellset OwnerCadence VirtuosoCalibre design softwareUNIXshell programminglithographymetrologyframe data outputtapeoutdesign rule verificationXOR analysissemiconductor manufacturingProcess Technology DevelopmentProduct Design teamsMask OperationsNPI setupframe revisionsframe cellsetCalibreshell scripting

Deal Breakers

No Cadence Virtuoso experience, No UNIX/shell scripting, Insufficient semiconductor manufacturing experience

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