About this role

This role involves leading physical design implementation of CPU architectures, ensuring timing closure, verification, and optimization from RTL to GDS in a high-performance semiconductor environment.

Key Responsibilities

Physical design implementation
Timing closure
Verification and signoff
Collaboration with EDA vendors
Methodology development

Technical Overview

The technical scope includes physical design flows such as synthesis, place and route, static timing analysis, clock tree synthesis, and verification, working closely with industry EDA tools and vendors.

Ideal Candidate

The ideal candidate is a highly experienced physical design engineer with over 12 years of experience in CPU design and physical implementation, capable of leading complex design flows from RTL to GDS, ensuring timing closure and verification.

Must-Have Skills

physical design implementationCPU designtiming closureverificationpower analysislayout verification

Nice-to-Have Skills

EDA toolshigh-speed designlow-power designstructured placementrouting

Tools & Platforms

EDA vendorsindustry EDA tools

Required Skills

Physical DesignRTLGDSSynthesisPlace and RouteClock Tree SynthesisFloor PlanningStatic Timing AnalysisPower/Clock DistributionReliabilityPower and Noise AnalysisFormal VerificationPower IntegrityLayout VerificationElectrical Rule CheckingStructural Design

Hard Skills

Physical DesignRTLGDSSynthesisPlace and RouteClock Tree SynthesisFloor PlanningStatic Timing AnalysisPower/Clock DistributionReliabilityPower and Noise AnalysisFormal VerificationPower IntegrityLayout VerificationElectrical Rule CheckingStructural Design

Soft Skills

leadershipcommunicationcollaborationproblem-solvingteam management

Industry & Role

Industry Semiconductors / Data Center

Job Function Lead physical design and verification of CPU microarchitectures

Keywords for Your Resume

Physical DesignRTLGDSSynthesisPlace and RouteClock Tree SynthesisFloor PlanningStatic Timing AnalysisPower/Clock DistributionReliabilityPower and Noise AnalysisFormal VerificationPower IntegrityLayout VerificationElectrical Rule CheckingStructural DesignCPU designtiming closureverificationpower analysislayout verification

Deal Breakers

Lack of extensive physical design experience, No background in CPU or high-speed design, Inability to lead a team, No experience with industry EDA tools

Senior Physical Design Integration Engineer

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