Position Details

Type Full-Time

Experience senior

Exp. Years Not specified

Education Not specified

Category Software Engineering

About this role

This role involves designing and developing advanced IPs for next-generation embedded products, owning the RTL design lifecycle from micro-architecture to silicon validation, with a focus on timing closure and physical design.

Key Responsibilities

Design RTL and micro-architecture
Drive full ASIC development lifecycle
Develop timing constraints and perform static timing analysis
Integrate IP blocks into SOCs
Collaborate on physical design aspects

Technical Overview

The position requires expertise in Verilog RTL coding, ASIC/SOC design, industry-standard EDA tools like PrimeTime and Tempus, and integration of IP blocks into full-chip SOCs, with physical design collaboration.

Ideal Candidate

The ideal candidate is a senior ASIC/SOC designer with extensive experience in RTL coding, timing closure, and physical design, with multiple tape-outs and strong ownership skills. They excel in Verilog and industry-standard EDA tools, and can mentor junior engineers.

Must-Have Skills

Verilog RTL codingASIC/SOC designtiming closurephysical design awarenessRTL design lifecycle

Nice-to-Have Skills

Physical design collaborationScripting for automationIndustry-standard tools

Tools & Platforms

PrimeTimeTempusAMBA protocols

Required Skills

VerilogRTL designASIC designtiming closurephysical designsynthesisstatic timing analysisPrimeTimeTempusAMBA protocolsPythonPerlTclmicro-architecturesilicon bring-up

Hard Skills

VerilogRTL designMicro-architectureTiming closurePhysical designSynthesisSTAPrimeTimeTempusAMBA AXIAHBAPBPCIeCXLPythonPerlTcl

Soft Skills

collaborationmentoringownershipproblem-solvingcommunication

Industry & Role

Industry Semiconductors & Electronics

Job Function ASIC/SoC RTL design and integration for embedded products

Role Subtype ASIC Design Engineer

Tech Domains Active Directory, Microsoft 365, Azure, Amazon Web Services, Linux

Keywords for Your Resume

RTL designASIC designVerilogtiming closurephysical designSynthesisSTAPrimeTimeTempusAMBA AXICXLPythonPerlTclmicro-architecturesilicon bring-uptiming analysisverificationfull-chip integrationRTL codingVerilog RTLASICAMBA protocols

Deal Breakers

Lack of experience in RTL design, No ASIC/SOC design background, No experience with industry-standard tools like PrimeTime, No knowledge of physical design or timing closure, No experience with silicon bring-up

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Senior RTL Design Engineer

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