Senior UCIe PHY Expert, MLA Technology

Senior UCIe PHY expert role within Annapurna Labs (AWS UC) focused on defining, designing, validating, and operating UCIe-based machine learning silicon for Trainium servers. You will collaborate with architects and engineers, develop scalable tests/scripts, and lead data-driven debugging and reliability improvements for AWS data centers.

• Collaborate with architects, design teams, and software engineers on next generation ML chips
• Support debug and operations of previous ML chips in manufacturing and data center
• Dive deep into IP integration, packaging, silicon bring up, characterization, and validation of UCIe subsystems
• Independently develop scripts to execute operational and debug tasks at scale
• Lead data collection at scale to improve machine learning hardware reliability

Work involves hardware/software co-design for next-generation machine learning chips, with deep responsibility across UCIe subsystem integration, packaging, silicon bring-up, characterization, and validation. The role emphasizes fleet-wide issue debugging, operational excellence, and scalable test/data collection feeding reliability improvements on AWS EC2 and Trainium server platforms.

The ideal candidate is a senior hardware validation and bring-up engineer with deep experience in UCIe and SERDES, including IP integration, packaging, characterization, and validation for high-speed subsystems. They have led fleet-wide debugging and large-scale test development, partnering with vendors and internal design teams to collect and analyze data from manufacturing and AWS data centers.