About this role
This role is within AMD's SOC Verification Team and focuses on silicon design verification using UVM. You will create System Verilog testbenches, develop constrained-random and directed verification environments, and use SVA with formal tools to verify complex IP.
Key Responsibilities
- Create and enhance UVM/System Verilog verification environments
- Develop test plans for complex IP designs
- Use constrained-random/direct verification plus SVA and formal tools
- Debug tests with design engineers and close coverage
- Track verification quality metrics including pass rates, code coverage, and functional coverage
Technical Overview
You will own block-level test benches and contribute to subsystem-level verification, including performance verification and power aware verification. Responsibilities include coverage closure and verification quality metrics, plus coordination with RTL engineers for improvements like clock gating.
Ideal Candidate
The ideal candidate is a silicon design verification engineer experienced with UVM verification methodology and System Verilog testbenches. They can build constrained-random/direct verification environments, use System Verilog Assertions (SVA) with formal verification, and drive coverage closure using verification quality metrics like pass rates, code coverage, and functional coverage.
Must-Have Skills
UVM verification methodologySystem VerilogDesign testbenches in System Verilog and UVMCreate and enhance constrained-random and/or directed verification environmentsformally verify designs with System Verilog Assertions (SVA) and industry leading formal toolsDebug tests with design engineers to deliver functionally correct design blocks and close the coverageResponsible for verification quality metrics like pass ratescode coverage and functional coverage
Nice-to-Have Skills
Project level experience with design concepts and RTL implementationKnowledge of object oriented concepts and programming languages like System VerilogC++Hands on Python scripting for automationPrior design/verification industry experience is a plus with hands on experience on UVM
Tools & Platforms
UVMSystem VerilogSystem Verilog Assertions (SVA)formal toolsPython
Required Skills
silicon design verificationUVM verification methodologySystem Verilogblock level test benchconstrained-random verificationdirected verificationSystem Verilog Assertions (SVA)formal verificationformal toolscode coveragefunctional coveragepass ratesclock gatingRTLPython scriptingautomationC++
Hard Skills
silicon design verificationverification methodologyUVM verification methodologySystem Verilogblock level test benchsub system level verificationperformance verificationpower aware verificationtest planscomplex IP designsconstrained-random verification environmentsdirected verification environmentsSystem Verilog Assertions (SVA)formal verificationformal toolsdebugging tests with design engineerscoverage closureRTL engineersclock gatingverification quality metricspass ratescode coveragefunctional coveragecomputer organization/architecturedigital logic fundamentalsobject oriented conceptsC++Python scriptingautomationUVM
Soft Skills
team playerexcellent communication skillsstrong analytical and problem-solving skillswilling to learnready to take on problems
Keywords for Your Resume
Silicon Design EngineerSilicon Design Verification EngineerSOC Verification Teamsilicon design verificationUVM verification methodologySystem Verilogtestbenchblock level test benchsub system level verificationperformance verificationpower aware verificationtest plansconstrained-randomdirected verificationSystem Verilog Assertions (SVA)formal verificationformal toolscoveragecode coveragefunctional coveragepass ratesclock gatingRTLPythonC++
Deal Breakers
Must demonstrate hands-on experience with UVM verification methodology and System Verilog testbenches, Must demonstrate experience with System Verilog Assertions (SVA) and formal verification
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