Position Details

Type Full-Time

Experience mid

Exp. Years 3+ years

Education Bachelor's or Master's degree in computer engineering/Electrical Engineering

Category System Administration

About this role

This role involves verifying the functional correctness of advanced AMD/Xilinx programmable devices through simulation, debugging, and coverage analysis, ensuring high-quality silicon delivery.

Key Responsibilities

Verify silicon functionality
Develop test plans and testbenches
Debug RTL and gate simulations
Collaborate with design teams
Improve verification flows

Technical Overview

The technical environment includes Verilog, SystemVerilog, UVM, RTL simulation, and C/C++ programming for chip verification and validation.

Ideal Candidate

The ideal candidate is a mid-level verification engineer with strong experience in Verilog, SystemVerilog, UVM, and RTL simulation, capable of handling complex chip verification tasks across multi-site teams.

Must-Have Skills

VerilogSystemVerilogUVMC/C++Python

Nice-to-Have Skills

gate level simulationpower verificationreset verificationassertion-based verification

Tools & Platforms

VerilogSystemVerilogUVMRTL simulation

Required Skills

VerilogSystemVerilogUVMRTL simulationCC++Pythonverification methodologies

Hard Skills

VerilogSystemVerilogUVMCC++AssemblyPythonRTL simulationverification methodologies

Soft Skills

collaborativecommunicationanalytical thinkingproblem-solvingownership

Industry & Role

Industry Semiconductors & Chip Manufacturing

Job Function Validate the correctness of programmable silicon devices through simulation and verification methodologies

Role Subtype Verification Engineer

Tech Domains Verilog, SystemVerilog, RTL simulation, C, C++, Python

Keywords for Your Resume

Silicon Design Verification EngineerVerilogSystemVerilogUVMRTL simulationverificationASICchip designfunctional verificationdebug RTLpower verificationreset verificationassertionCC++Pythongate level simulation

Deal Breakers

Lack of Verilog or SystemVerilog experience, No UVM or verification methodology background, No ASIC or chip design experience

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