About this role
Senior ASIC/SoC design engineer responsible for end-to-end design and integration of AI networking ASICs, including chiplet-based architectures, PCIe/DMA subsystems, and security/boot initialization.
Key Responsibilities
- Lead SoC level design and integration of embedded subsystems
- Drive integration using SoC IP generation and configuration tools
- Design and integrate PCIe subsystems and DMA engines
- Own and review reset architecture, boot flows, and security initialization sequences
- Support chiplet-based SoC integration including die-to-die connectivity
Technical Overview
End-to-end ASIC/SoC development with architecture through silicon bring-up; RTL in SystemVerilog/Verilog; integration tools for NoC/AMBA/CSR; chiplet die-to-die connectivity
Ideal Candidate
The ideal candidate is a senior ASIC/SoC engineer with extensive hands-on experience from architecture through silicon bring-up, including PCIe/DMA, NoC/AMBA, and chiplet integration. Strong RTL proficiency (SystemVerilog/Verilog) and a track record delivering production silicon are essential.
Must-Have Skills
Significant hands-on experience in ASIC/SoC development from architecture through silicon bring-upExperience with embedded SoC architectures including CPUs and NoCs using AMBA protocols (AXI/AHB/APB)Strong experience with PCIe and DMA architecturesHands-on experience using and integrating SoC IP generation and configuration tools for NoCAMBA protocol conversionand CSR generationProficiency in RTL design using SystemVerilog / VerilogDemonstrated experience delivering production ASIC or SoC siliconAbility to collaborate effectively across hardwarefirmwareand software teams
Nice-to-Have Skills
Chiplet-based SoC architectures and die-to-die (C2C) connectivity standards such as UCIeBackground in AInetworkingor data center class ASICsExposure to secure boothardware root of trustor security IP integrationExperience with emulationFPGA prototypingor post silicon debuggingInterest in applying AI-based tools to improve designintegrationor debug productivity
Tools & Platforms
RTL simulation environmentsEmulation platformsPost-silicon debug toolsSystemVerilog Verilog tooling
Required Skills
SoC designRTL (SystemVerilog/Verilog)PCIeDMANoCAMBA (AXI/AHB/APB)chiplet integrationdie-to-die connectivity (UCIe)chiplet-based architecturessecurity IP integrationemulationpost-silicon bring-uplint/CDCsynthesis
Hard Skills
ASIC SoC designSystemVerilogVerilogPCIeDMA architecturesNoCAMBA (AXI/AHB/APB)chiplet-based SoCdie-to-die connectivityRTL designlint/CDCsynthesisemulationpost-silicon bring-upsecurity IP integrationreset architectureboot flowssecurity initialization sequences
Soft Skills
systems thinkingcross-functional collaborationproblem solvingleadershipcommunication
Keywords for Your Resume
smtsasic so c design engineersystemverilogverilogpciedmanocambaaxIuh gchipletdie-to-dieuciertl designsynthesisemulationpost silicon bring-upsecurity ipreset architectureboot flowschiplet integrationsecurity initializationasic designsoC design
Deal Breakers
Lack of substantial SoC/ASIC bring-up experience, No SystemVerilog/Verilog RTL experience, No exposure to PCIe/DMA or AMBA protocols
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