Position Details
About this role
Lead the design, integration, and tape-out of high-performance ASICs and SoCs for AWS ML acceleration hardware, ensuring timely delivery and optimal performance.
Key Responsibilities
- Lead SOC integration
- Drive tape-out milestones
- Ensure physical design quality
- Collaborate with architecture teams
- Optimize ASIC performance
Technical Overview
Involves RTL design, physical implementation, verification, and tape-out of custom silicon chips, with a focus on hardware acceleration and SOC integration.
Ideal Candidate
The ideal candidate is a senior hardware engineer with proven experience leading SOC and ASIC integration, tape-out processes, and physical design. Deep expertise in RTL design, timing closure, and CDC methodologies is required.
Must-Have Skills
Nice-to-Have Skills
Tools & Platforms
Required Skills
Hard Skills
Soft Skills
Industry & Role
Keywords for Your Resume
Deal Breakers
Lack of tape-out experience, No ASIC/SoC design background, Inexperience with RTL design, No physical design expertise
Get matched to jobs like this
Luna finds roles that fit your skills and career goals — no endless scrolling required.
Create a Free Profile