✦ Luna Orbit — Engineering (Non-Software)

Sr. Manager Design Verification Engineering

at Advanced Micro Devices

📍 Santa Clara, California, United States Hybrid Posted March 26, 2026
Type Full-Time
Experience senior
Exp. Years Not specified
Education Not specified
Category Engineering (Non-Software)

This role involves leading the verification of complex ASICs and SoCs, developing verification strategies, and ensuring silicon success. The engineer will oversee test plans, coverage closure, and collaborate across teams.

  • Lead verification team
  • Develop verification strategies
  • Oversee test plan creation
  • Ensure coverage closure
  • Collaborate with design teams

Focus on ASIC and SoC verification using SystemVerilog, verification methodologies, and automation tools. Responsible for test plan creation, coverage analysis, and debugging.

The ideal candidate is a senior verification engineer with extensive experience in ASIC and SoC verification, proficient in SystemVerilog, and capable of leading verification teams through successful silicon tape-outs. They possess strong technical guidance and collaboration skills.

Leading ASIC or SoC design verification teamsSystemVerilog expertiseVerification strategy developmentTest plan creation and reviewFunctional and code coverage closure
Automation initiativesVerification methodology improvementsPost-silicon debugProject coordination
SystemVerilogVerification toolsCAD automation tools
ASIC verificationSystemVerilogverification strategiestest planfunctional coveragedebugproject managementleadership
SystemVerilogASIC verificationSoC verificationVerification strategiesTest plan creationFunctional coverageCode coverageDebuggingProject managementLeadership
LeadershipMentorshipTechnical guidanceCollaborationCommunicationProblem-solvingTime management
Industry Semiconductors & Electronics
Job Function Leading ASIC verification and ensuring silicon quality
Role Subtype Systems Verification Engineer
Tech Domains Active Directory, Verification tools
ASIC verificationSystemVerilogSoC verificationVerification strategiesTest planFunctional coverageCode coverageDebuggingProject managementLeadershipASICVerification engineerSilicon successDFXDFDverification strategiestest planfunctional coveragedebuggingproject managementlead verification teamsilicon success

Lack of ASIC verification leadership experience, No SystemVerilog expertise, Inability to lead verification teams, No experience with verification methodologies

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