✦ Luna Orbit — Engineering (Non-Software)

Sr. Package Layout Engineer, Annapurna Labs - AI Silicon Packaging

at Amazon.com

📍 US, TX, Austin Unknown Posted March 24, 2026
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Position Details

Type Full-Time
Experience senior
Exp. Years 5+ years
Education Not specified
Category Engineering (Non-Software)

About this role

This role involves leading the physical design of advanced IC packages, including 2.5D and 3D architectures, ensuring manufacturability, and collaborating with cross-disciplinary teams to deliver high-performance semiconductor solutions.

Key Responsibilities

  • Lead package layout cycle
  • Drive physical implementation
  • Define and optimize floorplans
  • Perform detailed routing
  • Coordinate with manufacturing teams

Technical Overview

Focus on physical IC layout, advanced packaging architectures like CoWoS and EMIB, RDL routing, TSVs, and verification, utilizing EDA and DFM tools.

Ideal Candidate

The ideal candidate is a senior IC packaging engineer with extensive experience in advanced packaging architectures, physical design, and verification processes, capable of leading complex IC layout projects.

Must-Have Skills

Experience with advanced IC packagingPhysical design expertiseKnowledge of DFM and verification

Nice-to-Have Skills

Experience with CoWoSEMIBKnowledge of silicon interposersExperience with ASIC physical design

Tools & Platforms

EDA toolsDFM toolsVerification tools

Required Skills

IC package designphysical designIC layout2.5D interposer3D-ICfan-out wafer-level packagingsilicon bridge technologiesbump/pad assignmentRDL routingTSVmicroviasPTH viaspackage stack-upDFMphysical verificationDRCEDA tools

Hard Skills

IC package designPhysical designIC layout2.5D interposer3D-ICFan-out wafer-level packagingSilicon bridge technologiesBump/pad assignmentRDL routingTSVMicroviasPTH viasPackage stack-upDFMPhysical verificationDRCEDA tools

Soft Skills

LeadershipProject managementCross-team collaborationProblem-solvingAttention to detail

Industry & Role

Industry Semiconductors & Hardware
Job Function Lead physical design of advanced IC packages for next-generation chips
Role Subtype Package Layout Engineer
Tech Domains Semiconductors & Hardware

Keywords for Your Resume

IC package designphysical designIC layout2.5D interposer3D-ICfan-out wafer-level packagingsilicon bridge technologiesbump/pad assignmentRDL routingTSVmicroviasPTH viaspackage stack-upDFMphysical verificationDRCEDA tools

Deal Breakers

Lack of experience with advanced IC packaging, No knowledge of DFM or verification tools, Inexperience with 2.5D/3D packaging technologies

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