Position Details
About this role
Annapurna Labs is seeking a Physical Design Engineer to lead the physical implementation of custom silicon chips for AWS data centers, ensuring high quality and performance.
Key Responsibilities
- Drive physical implementation
- Collaborate with RTL designers
- Perform synthesis and place & route
- Conduct timing and physical verification
- Support high-quality chip delivery
Technical Overview
The role involves RTL-to-GDSII physical design, scripting, physical verification, and sign-off activities using industry-standard EDA tools, with a focus on high-performance, low-power chip design.
Ideal Candidate
The ideal candidate is a mid to senior ASIC physical design engineer with extensive experience in RTL-to-GDSII flow, scripting, and physical verification. They should have strong collaboration skills and a background in sign-off activities and IP integration.
Must-Have Skills
Nice-to-Have Skills
Tools & Platforms
Required Skills
Hard Skills
Soft Skills
Industry & Role
Keywords for Your Resume
Deal Breakers
Less than 6 years of ASIC physical design experience, Lack of scripting skills (Python, Perl, Bash, PowerShell), No experience with EDA tools or sign-off activities
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