✦ Luna Orbit — Cloud & Infrastructure

Sr. Physical Design Verification Engineer, Annapurna Labs

at Amazon.com

📍 US, CA, Cupertino Onsite Posted April 03, 2026
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Position Details

Type Full-Time
Experience senior
Exp. Years 7+ years
Education BS in Electrical Engineering or Computer Science, or related field with 10+ years experience, or MS with 7+ years
Category Cloud & Infrastructure

About this role

Senior ASIC physical design verification engineer focused on ensuring quality and manufacturability of complex semiconductor designs through physical verification processes and integration methodologies.

Key Responsibilities

  • Define, execute and optimize physical verification methodologies
  • Drive chip-level sign-off
  • Perform DRC/LVS/PERC verification and fill insertion
  • Debug issues with layout/design teams
  • Interface with foundries for rule deck updates

Technical Overview

Scope includes DRC/LVS/PERC verification, fill insertion, tape-out readiness, and backend physical design flows using Calibre, IC Validator, and PVS, with Innovus as the primary backend tool for advanced nodes.

Ideal Candidate

The ideal candidate is a senior ASIC physical design verification engineer with 7+ years of combined experience in physical verification and backend flows, proficient with Calibre/IC Validator/PVS and tape-out discipline, and able to mentor junior engineers. They should be comfortable working onsite in Cupertino and collaborating with foundries to update rule decks and resolve violations for advanced nodes (5nm+).

Must-Have Skills

PythonPerlBS + 10yrs or MS + 7yrs in EE/CSor related field5+ in physical verification for advanced technology nodesCalibreIC ValidatorPVSLVSDRCPERCBackend physical design flows (FC/Innovus)

Nice-to-Have Skills

5nm or below node experienceDFM methodologiesESD/EM/IR drop reliability verificationlayout design or custom IC developmentleadership principles alignment

Tools & Platforms

CalibreIC ValidatorPVSInnovusFCInnovus

Required Skills

['physical verification''DRC''LVS''PERC''Calibre''IC Validator''PVS''FPGA''backend physical design flows''Innovus''Python''Perl''5nm''DFM''ESD''IR drop''tape-out''foundries''rule deck''waivers''mentoring']

Hard Skills

PythonPerlDRCDesign Rule CheckingLVSPERCProgrammable Electrical Rule CheckCalibreIC ValidatorPVSFill insertionTape-outBackend physical design flowsInnovusFC/Innovus5nmDFMESDEMIR drop

Soft Skills

communicationcollaborationmentoringproblem-solving

Industry & Role

Industry Semiconductors
Job Function Ensure quality and manufacturability of ASIC designs through physical verification and integration
Role Subtype Physical Design Engineer
Tech Domains Python, Amazon Web Services, Linux, Kubernetes, SQL / PostgreSQL

Keywords for Your Resume

physical designasic physical designphysical verificationcalibreic validatorpvslvsdr cpercfill insertiontape-outbackend physical design flowsInnovusfc/innovuspythonperldn od - tape-outassembly silicondigital and custom ic5nmdfmesdemir dropfoundriesrule deckwaiversmanufacturabilitymentoringCalibreIC ValidatorPVSDRCLVSPERCFill insertionPythonTape-out

Deal Breakers

No experience with advanced node physical verification (5nm or below), Lack of Python/Perl scripting in verification workflows, unwillingness to work onsite in Cupertino

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