✦ Luna Orbit — Engineering (Non-Software)

Sr. Signal Integrity / Power Integrity Engineer, Annapurna Labs, ML Packaging

at Amazon.com

📍 US, TX, Austin Unknown Posted March 13, 2026
Type Not Specified
Experience senior
Exp. Years Not specified
Education Not specified
Category Engineering (Non-Software)

This role involves designing and validating high-speed ASICs, performing SI/PI analysis, and troubleshooting manufacturing and signal integrity issues in hardware development for AWS data centers.

  • Perform high-speed channel simulations
  • Conduct SI/PI analysis
  • Utilize simulation tools
  • Work on PCIe protocols
  • Identify manufacturing issues

Focus on ASIC design, high-speed signal integrity, power integrity, simulation tools, and hardware troubleshooting to ensure robust hardware performance.

The ideal candidate is a senior hardware engineer with expertise in signal and power integrity, ASIC design, and high-speed interface analysis. They are experienced with simulation tools and troubleshooting complex SI/PI challenges in hardware development.

Experience with SI/PI analysisASIC design knowledgeSimulation tools (ADSMATLABCadenceHFSS)High-speed interface expertiseTroubleshooting skills
Experience with AWS hardwareMentorshipDesign validation
ADSMATLABCadenceHFSS
Signal IntegrityPower IntegrityASICHigh-speed channel simulationSI/PI analysisSimulation toolsPCIe protocolsJitter analysisHardware designManufacturing issues
Signal IntegrityPower IntegrityASIC designHigh-speed channel simulationSI/PI analysisSimulation toolsPCIe protocolsJitter analysisHardware designManufacturing issues
CommunicationTeamworkDecisivenessCollaborationProblem-solving
Industry Semiconductors / Hardware
Job Function Design and validate high-speed ASIC hardware
Signal IntegrityPower IntegrityASICHigh-speed channel simulationSI/PI analysisSimulation toolsPCIe protocolsJitter analysisHardware designManufacturing issuesTroubleshootingAWS hardwareElectromagnetic compatibilityHigh-speed interfacesDesign validation

Lack of experience with SI/PI analysis, No ASIC design background, Inexperience with simulation tools (ADS, MATLAB, Cadence, HFSS), No understanding of high-speed interfaces

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