✦ Luna Orbit — Cloud & Infrastructure

Sr. Substrate CAD Layout Eng, Annapurna Labs, Machine Learning Hardware

at Amazon.com

📍 US, CA, Cupertino Unknown Posted March 18, 2026
Type Not Specified
Experience mid
Exp. Years Not specified
Education Not specified
Category Cloud & Infrastructure

Annapurna Labs is seeking a Senior Substrate CAD Layout Engineer to contribute to next-generation ML ASIC development, focusing on substrate and PCB design, placement, routing, and fabrication processes.

  • Design substrate and PCB layouts
  • Coordinate with fabrication vendors
  • Develop schematics
  • Manage ECO processes
  • Support high-volume manufacturing

The role involves hardware design, PCB layout, schematic development, and working with fabrication vendors, utilizing CAD and EDA tools for silicon and circuit design.

The ideal candidate is an experienced substrate and PCB layout engineer with knowledge of silicon and hardware design, capable of contributing to high-volume manufacturing and chip development projects.

Substrate/PCB designplacementroutingschematic developmentfabrication knowledge
assemblyECO managementtest and fabricationhigh-volume manufacturing
PLM systemEDA toolsCAD software
substrate designpcb layoutplacementroutingschematic developmentfabricationassemblyECO managementsilicon design
Substrate designPCB layoutplacementroutingconstraint managementschematic developmentfabricationassemblyECO managementsilicon design
collaborationproblem-solvingattention to detailcommunicationteamwork
Industry Technology
Job Function Design and implement substrate and PCB layouts for advanced silicon hardware
Role Subtype Infrastructure Engineer
Tech Domains Silicon design, PCB design, EDA tools
Substrate designPCB layoutplacementroutingschematic developmentfabricationassemblyECO managementsilicon designhardware designASICML hardwareintegrated circuitsPCB manufacturingchip designsubstrate designpcb layout

Lack of PCB or substrate design experience, No familiarity with fabrication processes, Unfamiliar with schematic development, No experience with high-volume manufacturing

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