Position Details

Type Not Specified

Experience mid

Exp. Years Not specified

Education Not specified

Category Engineering (Non-Software)

About this role

This role involves leading the physical design of high speed SRAM and other chip components, collaborating with RTL and architecture teams to optimize performance and power in advanced FinFET technologies.

Key Responsibilities

Serve as technical lead for SRAM design
Collaborate on physical implementation
Optimize power and performance
Modify RTL for timing
Ensure design closure

Technical Overview

The position covers VLSI physical implementation, RTL modification, timing and power analysis, and chip architecture in FinFET process nodes, utilizing Verilog and physical design tools.

Ideal Candidate

The ideal candidate is a mid-level VLSI physical design engineer with experience in high speed SRAM, chip architecture, and RTL design using Verilog. They should be skilled in physical implementation, timing, and power optimization, capable of collaborating across design teams.

Must-Have Skills

Experience with high speed SRAM designKnowledge of computer architectureVerilog RTL modificationPhysical design collaborationTiming and power optimization

Nice-to-Have Skills

Chip level floor planningBus/pin planningClock tree synthesisParasitic extractionPhysical verification

Tools & Platforms

VerilogRTLPhysical design tools

Required Skills

VLSIPhysical DesignRTLVerilogTiming AnalysisPower OptimizationFloor PlanningChip DesignSystem ArchitectureHigh Speed SRAM

Hard Skills

VLSIPhysical DesignRTLVerilogTiming AnalysisPower OptimizationFloor PlanningChip DesignSystem ArchitectureHigh Speed SRAM

Soft Skills

Analytical SkillsProblem SolvingCollaborationCommunicationAdaptability

Industry & Role

Industry Technology

Job Function Design and optimize high speed SRAM within chip architecture

Role Subtype VLSI Design Engineer

Tech Domains Verilog, RTL, Physical Design, System Architecture

Keywords for Your Resume

VLSIPhysical DesignRTLVerilogTiming AnalysisPower OptimizationFloor PlanningChip DesignSystem ArchitectureHigh Speed SRAMPhysical verificationClock tree synthesisParasitic extractionDesign collaborationASIC designHardware designDigital circuitsFinFET technologiesTiming closurephysical designtiming analysispower optimizationfloor planningchip designsystem architecturehigh speed sram

Deal Breakers

Lack of experience with high speed SRAM design, No knowledge of physical design tools or RTL, Inability to modify Verilog RTL for timing or power

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