✦ Luna Orbit — System Administration

Staff Engineer, Physical Design

at Analog Devices

📍 3 Locations Unknown Posted March 24, 2026
Type Full-Time
Experience senior
Exp. Years 10+ years
Education Bachelor's or Master's in EE/ECE
Category System Administration

This role involves developing and verifying physical design for advanced semiconductor chips, focusing on digital implementation, physical verification, and tape out readiness.

  • Floorplan development
  • Power and clock distribution
  • Physical verification
  • Synthesis and timing closure
  • Tape out preparation

The environment includes VLSI design, ASIC physical implementation, using tools like Cadence, GDSII, and scripting languages such as Tcl, Perl. The focus is on 40nm digital design processes.

The ideal candidate is a highly experienced physical design engineer with over 10 years in digital implementation, familiar with advanced semiconductor design methodologies, scripting, and physical verification tools. They should possess strong technical ownership and teamwork skills.

B.Tech / M.Tech in EE/ECE10+ years of experiencedigital implementationFloor planningplace and route40nm digital implementationscripting skills (TclSKILLPerl)
Cadence tool experiencePerforce/MethodicsCPF/UPF methodologyCadence virtuosofoundry rulesGDS2 database
CadencePerforceMethodicsCadence virtuoso
Floor planningplace and routeCTSSTAECO methodologyPower analysisPhysical design verificationScripting (TclSKILLPerl)Cadence toolsPerforceMethodicsGDS2Tape out
Floor planningplace and routeCTSSTAECO methodologyPower analysisPhysical design verificationsynthesistiming constraints40nm digital implementationTclSKILLPerlCadence toolPerforceMethodicsCPFUPFCadence virtuosoGDS2Tape out
inter-personalteamworkcommunicationresponsibilitytechnical ownership
Industry Semiconductors / Electronics
Job Function Physical design engineering for semiconductor chips
Role Subtype Systems Administrator
Tech Domains Active Directory, Microsoft 365, Azure, Kubernetes, Linux, Windows Server, ITSM / ServiceNow, SAP, Oracle
physical designdigital implementationfloor planningplace and routeCTSSTAECO methodologypower analysisphysical design verification40nmscriptingTclSKILLPerlCadencePerforceMethodicsGDS2Tape outtiming constraints

Less than 10 years of experience, Lack of experience with 40nm digital implementation, No scripting skills (Tcl, SKILL, Perl)

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