About this role
Broadcom is hiring a Staff Memory Circuit Design Engineer to support an elite memory team building memory compilers and custom memory macros. The role covers transistor-level design, simulation, physical macro integration, characterization flow automation, and silicon correlation/debug.
Key Responsibilities
- Analyze different memory architectures and highlight tradeoffs
- Design and build memory or circuit blocks at the gate or transistor level
- Simulate and analyze using transistor level simulators and perform post-layout simulations
- Develop and integrate characterization flow to extract timing and power information and automate with scripts
- Specify and verify behavioral and physical memory models, define silicon test plan, and correlate/debbug silicon issues
Technical Overview
You will analyze memory architectures, design memory/circuit blocks at gate/transistor level, and run transistor-level simulation. The work includes layout extraction, post-layout simulation/verification, floorplanning physical implementation with leafcell integration, and characterization flows to extract timing and power, supported by Python automation scripts and behavioral/physical memory model specification with DFT considerations.
Ideal Candidate
The ideal candidate is a memory circuit design engineer with strong experience developing memory compilers and/or custom memory macros, including gate/transistor-level design and transistor-level simulation. They are comfortable with post-layout verification, floorplan physical implementation with leafcell integration, and building characterization flows that extract timing and power, with strong scripting in Python and good debugging experience tied to silicon test plan correlation.
Must-Have Skills
Knowledge in development of memory compilers or custom digital circuits of all types; SRAMsRegister-filesMulti-portsROMetc...Good understanding of transistor level circuit behavior and device physicsGood understanding of signal integrityEM/IRand reliability analysisUnderstanding of memory behavioral and physical modelsUnderstanding of DFT schemes and chip level integrationProficient in running simulatorswriting automation scriptsGood proficiency in Python scripting language is a strong positiveGood communicationinterpersonaland leadership skillsRequires a BS in Electrical Engineering and 8+ years of related experience (or MS/PhD alternatives)
Nice-to-Have Skills
Familiarity with test setupssilicon testing and debug is a plusProficiency in running simulatorswriting automation scriptsand are tools savvy
Required Skills
Memory compilerscustom macrosmemory architectures analysisgate or transistor level circuit designtransistor level simulatorsextract layoutpost-layout simulations and verificationfloorplan physical implementationleafcell layout integrationcharacterization flowextract timing and power informationautomation scriptsspecify and verify behavioral and physical memory modelsDFT schemeschip level integrationsilicon test plancorrelate silicon to simulation datadebug silicon issuesPython scripting languagesignal integrityEM/IRreliability analysissilicon testing
Hard Skills
Memory compilersCustom macrosMemory architecture analysisAnalyze memory architecturesGate or transistor level designDesign and build memory or circuit blocks at the gate or transistor levelTransistor level simulatorsPost-layout simulations and verificationLayout extractionFloorplan physical implementationLeafcell layout integrationPhysical macro buildCharacterization flowExtract timing and power informationScript development to automate characterization flowSimulationsVerificationBehavioral and physical memory modelsSpecify and verify behavioral and physical memory modelsDFT schemesChip level integrationSilicon test planCorrelate silicon to simulation dataDebug silicon issuesPython scriptingRunning simulators
Soft Skills
Good communicationInterpersonal skillsLeadership skillsEnergetic and passionateMotivated and self-drivenGood at multi-tasking
Keywords for Your Resume
Staff Memory Circuit Design Engineermemory design engineersCentral Engineering Groupmemory compilerscustom macrosmemory architecturesgate or transistor leveltransistor level simulatorslayout extractionpost-layout simulationsfloorplan physical implementationleafcell layout integrationphysical macrocharacterization flowextract timing and power informationautomation scriptsbehavioral and physical memory modelsDFT schemeschip level integrationsilicon test plancorrelate silicon to simulation datadebug silicon issuesPython scripting languageSRAMsRegister-filesMulti-portsROMsignal integrityEM/IRreliability analysisElectrical Engineering8+ years
Deal Breakers
Requires BS in Electrical Engineering and 8+ years of related experience (or MS/PhD alternatives as specified), Must have knowledge in development of memory compilers or custom digital circuits; SRAMs, Register-files, Multi-ports, ROM, etc.
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