About this role
This role is a Staff Memory Circuit Design Engineer position focused on developing memory compilers and custom memory macros at advanced process nodes. You will design at gate or transistor level, perform simulations and post-layout verification, integrate characterization flows, and help debug silicon issues.
Key Responsibilities
- Design memory or circuit blocks at gate or transistor level
- Simulate and analyze using transistor level simulators and perform post-layout simulations and verification
- Extract layout and integrate leafcell layout integration for physical macros
- Integrate characterization flow to extract timing and power information
- Specify and verify memory behavioral and physical models and correlate silicon test plan to simulations
Technical Overview
The technical scope spans transistor-level circuit design and analysis, layout extraction and post-layout simulations, and characterization flow integration to extract timing and power. The role also includes specifying behavioral and physical memory models, working with DFT schemes and chip-level integration, and correlating silicon test results with simulation data, supported by Python automation.
Ideal Candidate
The ideal candidate is a staff-level memory circuit design engineer with strong experience building memory compilers and custom macros across leading-edge process technology. They are expert in transistor-level circuit design and simulation, post-layout verification, and integrating characterization flows to extract timing and power. They also have solid knowledge of memory behavioral/physical models, DFT schemes, silicon test correlation, and Python-based automation scripting.
Must-Have Skills
Knowledge in development of memory compilers or custom digital circuits of all types; SRAMsRegister-filesMulti-portsROMetc...Good understanding of transistor level circuit behavior and device physicsGood understanding of signal integrityEM/IRand reliability analysisUnderstanding of memory behavioral and physical modelsUnderstanding of DFT schemes and chip level integrationProficient in running simulatorswriting automation scriptsGood proficiency in Python scripting languageGood communicationinterpersonaland leadership skillsRequires a BS in Electrical Engineering and 8+ years of related experience (or MS/PhD alternatives)
Nice-to-Have Skills
Familiarity with test setupssilicon testing and debug is a plus
Tools & Platforms
transistor level simulatorsPython
Required Skills
memory compilerscustom macrosmemory architecturesSRAMsRegister-filesMulti-portsROMgate or transistor level designtransistor level simulatorslayout extractionpost-layout simulations and verificationfloorplan physical implementationleafcell layout integrationcharacterization flowextract timing and power informationscripting automationPython scriptingbehavioral and physical memory modelsDFT schemeschip level integrationsilicon test plancorrelate silicon to simulation datadebug silicon issuessignal integrityEM/IRreliability analysistiming diagramsbehavioral description
Hard Skills
memory designmemory compilerscustom macrosmemory architectures analysiscircuit blocks design at the gate levelcircuit blocks design at the transistor levelsimulate and analyze circuit design using transistor level simulatorslayout extractionpost-layout simulations and verificationfloorplan physical implementationleafcell layout integrationintegrate characterization flowextract timing informationextract power informationscripts to automate characterization flowsimulationsand verificationspecify and verify behavioral modelsspecify and verify physical memory modelsDFT schemeschip level integrationsilicon test plancorrelate silicon to simulation datadebug silicon issuesPython scriptingtransistor level circuit behavior and device physicssignal integrityEM/IRreliability analysistiming diagramsbehavioral descriptionsilicon testing
Soft Skills
Good communicationinterpersonal skillsleadership skillsMotivatedself-drivenmulti-tasking
Keywords for Your Resume
Staff Memory Circuit Design Engineermemory design engineersmemory compilerscustom macrosmemory architecturesSRAMsRegister-filesMulti-portsROMgate or transistor leveltransistor level simulatorslayout extractionpost-layout simulationsverificationfloorplan physical implementationleafcell layout integrationcharacterization flowtiming informationpower informationPython scriptingautomation scriptsbehavioral and physical memory modelsDFT schemeschip level integrationtest plansilicon testingcorrelate silicon to simulation datadebug silicon issuessignal integrityEM/IRreliability analysistiming diagramsbehavioral description
Deal Breakers
BS in Electrical Engineering and 8+ years of related experience (or MS/PhD equivalents as stated)
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