About this role
Staff Research Scientist focused on AI-hardware co-design, bridging advanced AI algorithms with silicon implementations and optimizing compute across architectures from MCUs to accelerators.
Key Responsibilities
- ['Strategic problem definition and opportunity identification for AI-hardware co-design
- Architectural design to validated proof-of-concept', 'Feasibility analysis with high-fidelity simulation to quantify memory/dataflow/precision impact', 'Drive simultaneous optimization of algorithms and hardware; map neural graphs to silicon', 'Mentor junior engineers and contribute to thought leadership', 'Publish results and maintain awareness of evolving AI hardware landscape']
Technical Overview
Role centers on system-level hardware architecture, memory hierarchy, dataflow, and precision management; involves high-fidelity simulation, cycle-accurate modeling, and proof-of-concept work for AI compute substrates.
Ideal Candidate
The ideal candidate is a staff research scientist with a PhD in Computer Architecture, 3+ years applying arch to AI hardware, and hands-on RTL and hardware-aware DL experience with a track record of published work.
Must-Have Skills
PhD specialized in Computer Architecture or Integrated Circuit Design for AI workloads3+ years of industry experience applying architectural principles to real-world engineering constraintsProven Silicon Execution: taped out a complex SoC or a custom AI acceleratorDeep System-Level Hardware Expertise: memory hierarchiesdataflowand precision managementEdge AI & Model Optimization: hardware-aware DLmapping graphs to siliconquantizationProficiency in modern frameworks (PyTorchJAX) and ability to train or fine-tune modelsHands-on RTL Experience: Verilog/SystemVerilog; ChiselPyMTL is a strong plusStrong publication record in top conferences and/or journals
Nice-to-Have Skills
Verilog/SystemVerilog hands-on RTL experienceChiselPyMTLProof-of-concept development for AI compute substratesPublication track record
Tools & Platforms
PyTorchJAXVerilogSystemVerilogChiselPyMTL
Required Skills
PhD in Computer Architecture or Integrated Circuit Design for AI workloads; 3+ years industry experience in architectural principles; proven silicon execution (taped out SoC or AI accelerator); memory hierarchy and dataflow expertise; edge AI and hardware-aware DL; PyTorch and JAX; RTL experience (Verilog/SystemVerilogChiselPyMTL); strong publication record
Hard Skills
PythonPyTorchJAXVerilogSystemVerilogChiselPyMTLMemory hierarchyDataflowQuantization (INT8mixed-precision)High-fidelity simulationCycle-accurate simulationTape-outHardware architectureEdge AI
Soft Skills
LeadershipMentoringCollaborationCommunicationProblem-solving
Keywords for Your Resume
staff research scientistai-hardware co-designarchitecturememory hierarchydataflowquantizationedge aipytorchjaxverilogsystemverilogchiselpymtlrtlSoCsiliconPhD in Computer Architecture3+ yearsAI hardwareco-designPyTorchJAXVerilogSystemVerilogChiselPyMTL
Deal Breakers
Lack of PhD in relevant field, Less than 3 years of industry experience, No RTL experience or publications
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