Position Details

Salary $141K – $200K USD / year

Type Full-Time

Experience mid

Exp. Years 4+ years

Education Bachelor's in Electrical Engineering, Computer Engineering, or Computer Science

Category IT Support & Helpdesk

About this role

This role involves verifying complex ASIC and SoC designs through functional verification, developing test environments, and collaborating with design teams to ensure design correctness.

Key Responsibilities

Perform ASIC verification
Develop verification plans
Build testbenches
Debug design issues
Collaborate with design teams

Technical Overview

The position requires expertise in digital ASIC verification, SystemVerilog, UVM methodology, emulation, and system simulation tools to validate complex integrated circuits.

Ideal Candidate

The ideal candidate is a verification engineer with over 4 years of experience in ASIC or SoC verification, proficient in SystemVerilog and UVM, capable of developing verification environments and debugging complex digital designs.

Must-Have Skills

Bachelor's degree in Electrical EngineeringComputer Engineeringor Computer Science4+ years of ASIC/SoC verification experienceKnowledge of SystemVerilog and UVM methodology

Nice-to-Have Skills

Understanding of digital design fundamentalsExperience with emulation and system simulationKnowledge of power and performance analysis

Tools & Platforms

SystemVerilogUVMEmulation toolsSimulation tools

Required Skills

ASIC verificationSystemVerilogUVMDigital designSystem simulationEmulationVerification plansTest benchesDebuggingPower analysisPerformance analysis

Hard Skills

ASIC verificationSystemVerilogUVMDigital designSystem simulationEmulationVerification plansTest benchesDebuggingPower analysisPerformance analysis

Soft Skills

Problem-solvingCollaborationCommunicationAdaptabilityEagerness to learn

Industry & Role

Industry Technology / Semiconductors

Job Function ASIC/SoC verification and validation

Keywords for Your Resume

Verification EngineerASIC verificationSystemVerilogUVMDigital designSystem simulationEmulationVerification plansTest benchesDebuggingPower analysisPerformance analysis

Deal Breakers

Less than 4 years of verification experience, Lack of knowledge in SystemVerilog or UVM, No experience with emulation or system simulation

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