About this role
This role focuses on FPGA/ASIC verification to support first-pass silicon success. You will collaborate with architecture, IP, PD, and product engineering teams to plan tests, build UVM-based testbenches, and run regressions to debug functional and performance issues.
Key Responsibilities
- Collaborate with architects and hardware/firmware engineers to understand new features to be verified
- Develop test plan documentation across hardware, firmware, and driver use cases
- Code UVM based testbenches and verification components (monitors, scoreboard, checkers)
- Build directed and random verification tests
- Run regressions and debug test failures to ensure functional, performance, and implementation quality
Technical Overview
You will develop test plan documentation and code UVM-based verification components (monitors, scoreboard, checkers) to create directed and random tests. The work includes executing regressions, debugging test failures, and optionally improving simulation efficiency using acceleration and HLS tools/process. Protocol exposure may include PCIe, CXL, NVMe, or ethernet.
Ideal Candidate
The ideal candidate is a verification engineer with hands-on FPGA/ASIC verification experience using UVM-based testbenches. They are strong in Verilog and SystemVerilog, can build testbenches with monitors/scoreboards/checkers, run regressions, and debug failures to ensure functional, performance, and implementation quality.
Must-Have Skills
Code IP or SS level UVM based testbenchesverification components - monitorsscoreboardcheckersDevelop test plan documentationRun regressionsdebug test failures
Nice-to-Have Skills
Expert in developing UVM based verification frameworks and testbenchesScripting and automation of verification processes and flowsExposure to simulation profileefficiency improvementaccelerationHLS tools/processComfortable in python / perl and editing / maintaining scriptsExperience with PCIeCXLNVMe or ethernet protocolsExperience working in a team environment through the ASIC Project lifecycle from Planning to Tape OutGood Computer Architecturesystems knowledge
Required Skills
FPGAASICsUVMVerilogSystem Verilogtest plan documentationmonitorsscoreboardcheckersdirected and random verification testsregressionsdebug test failurespythonperlHLS tools/processASIC Project lifecyclePCIeCXLNVMeethernet protocols
Hard Skills
FPGAASICsfront-end design/integrationverification engineertest plan documentationUVM based testbenchesUVMmonitorsscoreboardcheckersdirected verification testsrandom verification testsregressionsdebug test failuresfunctional qualityperformance qualityimplementation qualityVerilogSystem VerilogObject Oriented programmingscripting and automation of verification processes and flowssimulation profileefficiency improvementaccelerationHLS tools/processComputer Architecturesystems knowledgepythonperlediting and maintaining scriptsASIC Project lifecyclePlanningTape OutPCIeCXLNVMeethernet protocols
Soft Skills
team playerexcellent communication skillscollaborating with engineers located in different sites/time zonesstrong analytical and problem-solving skillswillingness to learnready to take on problemswork independentlycross-site team environment
Keywords for Your Resume
Verification Engineer - FPGA/ASICFPGAASICsfront-end design/integrationUVMUVM based testbenchesVerilogSystem VerilogObject Oriented programmingtest plan documentationmonitorsscoreboardcheckersdirected and random verification testsregressionsdebug test failuressimulation profileefficiency improvementaccelerationHLS tools/processpythonperlASIC Project lifecyclePlanningTape OutPCIeCXLNVMeethernet protocols
Deal Breakers
Experience coding UVM based testbenches and verification components (monitors, scoreboard, checkers), Verilog and System Verilog verification experience
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